Low Power SRAM Design with Reduced Read/Write Time
نویسندگان
چکیده
This paper explores the design and analysis of Static Random Access Memories (SRAMs) which focusses on optimizing delay and power. CMOS SRAM cell consumes very less power and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. In this paper, 6T SRAM cell is implemented with reduced read and write time, delay and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing, to avoid this problem use optimized scaling techniques and further, get improve performance of the design.
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